H8SLASH3021 datasheet(484/712 Pages) RENESAS

484 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 460 of 684

REJ09B0352-0200

The flash memory block configuration is shown in table 15.3.

A total memory erase is carried out by erasing individual blocks in turn.

Bit:

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

Initial value:

R/W:

R/W

15.5.4

Erase Block Register 2 (EBR2)

EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is

initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,

when a low level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is

not set, even though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the

corresponding block can be erased. Other blocks are erase-protected. Only one of the bits of EBR1

and EBR2 combined can be set. Do not set more than one bit, as this will cause all the bits in both

EBR1 and EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must only be

written with 0. When on-chip flash memory is disabled, a read will return H'00, and writes are

invalid.

The flash memory block configuration is shown in table 15.3.

A total memory erase is carried out by erasing individual blocks in turn.

Note:

Bits 7 to 4 in this register must not be set to 1. If bits 7 to 4 are set when an EBR1/EBR2

bit is set, EBR1/EBR2 will be initialized to H'00.

Bit:

—

EB11

EB10

EB9

EB8

Initial value:

R/W:

R/W

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