H8SLASH3021 datasheet(485/712 Pages) RENESAS

485 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 461 of 684

REJ09B0352-0200

Table 15.3

Flash Memory Erase Blocks

Block (Size)

Addresses

EB0 (4 kB)

H'000000–H'000FFF

EB1 (4 kB)

H'001000–H'001FFF

EB2 (4 kB)

H'002000–H'002FFF

EB3 (4 kB)

H'003000–H'003FFF

EB4 (4 kB)

H'004000–H'004FFF

EB5 (4 kB)

H'005000–H'005FFF

EB6 (4 kB)

H'006000–H'006FFF

EB7 (4 kB)

H'007000–H'007FFF

EB8 (32 kB)

H'008000–H'00FFFF

EB9 (64 kB)

H'010000–H'01FFFF

EB10 (64 kB)

H'020000–H'02FFFF

EB11 (64 kB)

H'030000–H'03FFFF

15.5.5

RAM Emulation Register (RAMER)

RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating

real-time flash memory programming. RAMER initialized to H'F0 by a power-on reset and in

hardware standby mode. It is not initialized in software standby mode. RAMER settings should be

made in user mode or user program mode.

Flash memory area divisions are shown in table 15.4. To ensure correct operation of the emulation

function, the ROM for which RAM emulation is performed should not be accessed immediately

after this register has been modified. Normal execution of an access immediately after register

modification is not guaranteed.

Bit:

—

RAMS

RAM2

RAM1

RAM0

Initial value:

R/W:

R/W

Bits 7 to 4—Reserved: These bits always read 1.

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