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H8/3021 Datasheet(PDF) 487 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 487 Page - Renesas Technology Corp |
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487 / 712 page ![]() 15. ROM Rev.2.00 Mar. 22, 2007 Page 463 of 684 REJ09B0352-0200 15.5.6 Differences from H8/3039 F-ZTAT Group Table 15.5 Comparison of H8/3039F and H8/3022F H8/3039F H8/3022F Size 128 kbytes 256 kbytes Program/erase voltage Supplied from VCC Supplied from VCC Programming Programming unit 32-byte simultaneous programming 128-byte simultaneous programming Write pulse application method 150 μs × 4 + 500 μs × 399 30 μs × 6 + 200 μs × 994 (with 10 μs additional programming)* 1 Erasing Block configuration 8 blocks 1 kbyte × 4, 28 kbytes × 1, 32 kbytes × 3 12 blocks 4 kbytes × 8, 32 kbytes × 1, 64 kbytes × 3 EBR configuration EBR: H'FF42 7 EB7 6 EB6 5 EB5 4 EB4 3 EB3 2 EB2 1 EB1 0 EB0 EBR1: H'FF42 7 EB7 6 EB6 5 EB5 4 EB4 3 EB3 2 EB2 1 EB1 0 EB0 EBR2: H'FF43 7 — 6 — 5 — 4 — 3 EB11 2 EB10 1 EB9 0 EB8 RAM emulation RAM area 1 kbyte (H'FF800 to H'FFBFF) 4 kbytes (H'FE000 to H'FEFFF) Applicable blocks EB0 to EB3 EB0 to EB7 RAMCR configuration RAMCR: H'FF47 7 — 6 — 5 — 4 — 3 RAMS 2 RAM2 1 RAM1 0 — RAMER: H'FF47 7 — 6 — 5 — 4 — 3 RAMS 2 RAM2 1 RAM1 0 RAM0 Flash error FLER bit FLMSR: H'FF4D 7 FLER 6 — 5 — 4 — 3 — 2 — 1 — 0 — FLMCR2: H'FF41 7 FLER 6 — 5 — 4 — 3 — 2 — 1 — 0 — Flash memory characteristics Wait after SWE clearing — t CSWE specification must be met* 2 Boot mode Bit rate 9,600 bps, 4,800 bps 19,200 bps, 9,600 bps, 4,800 bps Boot area H'FEF10 to H'FF2FF H'FFDF10 to H'FFE70F User area H'FF300 to H'FFF0F H'FFE710 to H'FFFF0F |
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