H8SLASH3021 datasheet(491/712 Pages) RENESAS

491 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 467 of 684

REJ09B0352-0200

Automatic SCI Bit Rate Adjustment

Start

bit

Stop

bit

Low period (9 bits) measured (H'00 data)

High period

(1 or more bits)

When boot mode is initiated, the LSI measures the low period of the asynchronous SCI

communication data (H'00) transmitted continuously from the host. The SCI transmit/receive

format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of

the transmission from the host from the measured low period, and transmits one H'00 byte to the

host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end

indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception

cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.

Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be

a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 4,800,

9,600 or 19,200 bps*

1 to operate the SCI properly.

Table 15.7 shows host transfer bit rates and system clock frequencies for which automatic

adjustment of the LSI bit rate is possible. The boot program should be executed within this system

clock range.*

Table 15.7

System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible

Host Bit Rate

System Clock Frequency for Which Automatic Adjustment

of LSI Bit Rate is Possible (MHz)

4,800 bps

4 to 18

9,600 bps

8 to 18

19,200 bps

16 to 18

Notes: 1. Use a host bit rate setting of 4800, 9600, or 19200 bps only. No other setting should be

used.

2. Although the H8/3022 may also perform automatic bit rate adjustment with bit rate and

system clock combinations other than those shown in table 15.7, a degree of error will

arise between the bit rates of the host and the H8/3022, and subsequent transfer will

not be performed normally. Therefore, only combinations of bit rate and system clock

within the ranges shown in table 15.7 can be used for boot mode execution.

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