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H8/3021 Datasheet(PDF) 492 Page - Renesas Technology Corp

Part # H8/3021
Description  16-Bit Single-Chip Microcomputer
PDF  712 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/3021 Datasheet(HTML) 492 Page - Renesas Technology Corp

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15. ROM
Rev.2.00 Mar. 22, 2007 Page 468 of 684
REJ09B0352-0200
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an
area used by the boot program and an area to which the programming control program is
transferred via the SCI, as shown in figure 15.8. The boot program area cannot be used until the
execution state in boot mode switches to the programming control program transferred from the
host.
H'FFDF10
H'FFE710
H'FFFF0F
Boot program
area
Programming
control program
area
Note: The boot program area cannot be used until the programming control program transferred to
RAM switches to the execution state. Note also that the boot program remains in this area
in RAM even after control branches to the programming control program.
Figure 15.8 RAM Areas in Boot Mode (Mode 6)
Notes on Use of Boot Mode
1. When the H8/3022 comes out of reset in boot mode, it measures the low period of the input at
the SCI’s RXD
1 pin.
The reset should end with RXD
1 high.
After the reset ends, it takes about
100 states for the H8/3022 to get ready to measure the low period of the RXD
1 input.
2. In boot mode, if any data has been programmed into the flash memory (if all data is not H'FF),
all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
3. Interrupts cannot be used while the flash memory is being programmed or erased.
4. The RXD
1 and TXD1 lines should be pulled up on the board.
5. Before branching to the programming control program (in mode 6, H'FFE710 in the RAM
area), the H8/3022 terminates transmit and receive operations by the on-chip SCI (channel 1)
(by clearing the RE and TE bits to 0 in the serial control register (SCR)), but the adjusted bit



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