H8SLASH3021 datasheet(493/712 Pages) RENESAS

493 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 469 of 684

REJ09B0352-0200

rate value remains set in the bit rate register (BRR). The transmit data output pin, TXD

1 , goes

to the high-level output state (P9

1DDR = 1 in P9DDR, P91DR = 1 in P9DR).

The contents of the CPU's internal general registers are undefined at this time, so these

registers must be initialized immediately after branching to the user program. In particular,

since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be

specified for use by the user program.

The initial values of other on-chip registers are not changed.

6. Boot mode can be entered by setting pins MD

0 to MD2 and FWE in accordance with the mode

setting conditions shown in table 15.6, and then executing a reset-start.

On reset release (a low-to-high transition)*

1, the H8/3022 latches the current mode pin states

internally and maintains the boot mode state. Boot mode can be cleared by driving the FWE

pin low during the reset, then executing reset release*

1, but the following points must be noted.

a. When switching from boot mode to normal mode, the boot mode state within the chip must

first be cleared by reset input via the

RES pin. The RES pin must be held low for at least

20 system clock cycles.*

b. Do not change the input levels of the mode pins (MD

2 to MD0) or the FWE pin in boot

mode. To change the mode, the

RES pin must first be driven low to set the reset start.

Also, if a watchdog timer reset occurs in the boot mode state, the MCU’s internal state will

not be cleared, and the on-chip boot program will be restarted regardless of the mode pin

states.

c. Do not drive the FWE pin low during boot program execution or flash memory

programming/erasing*

7. If the mode pin and FWE pin input levels are changed from 0 V to VCC or from VCC to 0V

during a reset (while a low level is being input to the

RES pin), the MCU’s operating mode

will change. As a result, the state of ports with multiplexed address functions and bus control

output signals (

AS, RD, WR) may also change. Therefore, care must be taken to make pin

settings to prevent these pins from becoming output signal pins during a reset, or to prevent

collision with signals outside the MCU.

Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (t

MDS)

with respect to the reset release timing.

2. For further information on FWE application and disconnection, see section 15.11,

Flash Memory Programming and Erasing Precautions.

3. See section 4.2.2, Reset Sequence, and section 15.11, Flash Memory Programming and

Erasing Precautions. The reset period during operation is a minimum of 10 system

clock cycles for the H8/3022, H8/3021, and H8/3020 mask ROM versions, but a

minimum of 20 system clock cycles for the H8/3022 flash memory version.

H8/3021 Datasheet(PDF) 493 Page - Renesas Technology Corp

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