H8SLASH3021 datasheet(497/712 Pages) RENESAS

497 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 473 of 684

REJ09B0352-0200

Normal mode

On-board

programming mode

Software programming

disable state

Erase setup

state

Erase mode

Erase-verify

mode

SWE = 1

SWE = 0

FWE = 1

FWE = 0

E = 1

E = 0

Software

programming

enable

state

ESU = 1

ESU = 0

EV = 1

EV = 0

Program setup

state

Program mode

Program-verify

mode

P = 1

P = 0

**4

PV = 0

PV = 1

PSU = 1

PSU = 0

Notes: In order to perform a normal read of flash memory, SWE must be cleared to 0.

Also note that verify-reads can be performed during the programming/erasing process.

: Normal mode

: On-board programming mode

2. Do not make a state transition by setting/clearing multiple bits simultaneously.

3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing

through the software programming enable state.

4. After a transition from program mode to the program setup state, do not enter program mode without

passing through the software programming enable state.

Figure 15.10 State Transitions Caused by FLMCR1 Bit Settings

15.7.1

Program Mode

When writing data or programs to flash memory, the program/program-verify flowchart shown in

figure 15.11 should be followed. Performing program operations according to this flowchart will

enable data or programs to be written to flash memory without subjecting the device to voltage

stress or sacrificing program data reliability. Programming should be carried out 128 bytes at a

time.

Following the elapse of (t

sswe) µs or more after the SWE bit is set to 1 in flash memory control

data area, and the 128-byte data in the program data area in RAM is written consecutively to the

program address (the lower 8 bits of the first address written to must be H'00 or H'80). 128

consecutive byte data transfers are performed. The program address and program data are latched

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