H8SLASH3021 datasheet(499/712 Pages) RENESAS

499 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 475 of 684

REJ09B0352-0200

In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must

be H'00 or H'80.

2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer

should be used.

128-byte data transfer is necessary even when writing fewer than 128 bytes of data. H'FF data

must be written to the extra addresses.

3. Verify data is read in word units.

4. The write pulse is applied and a flash memory write executed while the P bit in FLMCR1 is

set. In the H8/3022F, write pulses should be applied as follows in the program/program-verify

procedure to prevent voltage stress on the device and loss of write data reliability.

a. After write pulse application, perform a verify-read in program-verify mode and apply a

write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write

bits in the 128-byte write data are read as 0 in the verify-read operation, the

program/program-verify procedure is completed. In the H8/3022F, the number of loops in

reprogramming processing is guaranteed not to exceed the maximum programming count

(N).

b. After write pulse application, a verify-read is performed in program-verify mode, and

programming is judged to have been completed for bits read as 0. The following processing

is necessary for programmed bits.

When programming is completed at an early stage in the program/program-verify

procedure:

If programming is completed in the 1st to 6th reprogramming processing loop, additional

programming should be performed on the relevant bits. Additional programming should

only be performed on bits which first return 0 in a verify-read in certain reprogramming

processing.

When programming is completed at a late stage in the program/program-verify procedure:

If programming is completed in the 7th or later reprogramming processing loop, additional

programming is not necessary for the relevant bits.

c. If programming of other bits is incomplete in the 128 bytes, reprogramming process should

be executed. If a bit for which programming has been judged to be completed is read as 1

in a subsequent verify-read, a write pulse should again be applied to that bit.

5. The period for which the P bit in FLMCR1 is set (the write pulse width) should be changed

according to the degree of progress through the program/program-verify procedure. For

detailed wait time specifications, see section 18.2.5, Flash Memory Characteristics.

H8/3021 Datasheet(PDF) 499 Page - Renesas Technology Corp