H8SLASH3021 datasheet(502/712 Pages) RENESAS

502 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 478 of 684

REJ09B0352-0200

Start

End of programming

End of Subroutine

Set SWE bit in FLMCR1

Wait (tsswe) μs

n = 1

m = 0

Sub-routine-call

See Note 6 for pulse width

Note 6: Write Pulse Width

Start of programming

Write Pulse subroutine

Set PSU bit in FLMCR1

Enable WDT

Set P bit in FLMCR1

Wait (tspsu) μs

Clear P bit in FLMCR1

Wait (tsp30 or tsp200) μs

Clear PSU bit in FLMCR1

Wait (tcp) μs

Disable WDT

Wait (tcpsu) μs

Write pulse application subroutine

Yes

Wait (tspv) μs

Wait (tspvr) μs

*5, *7

Write Pulse (Additional programming)

Set PV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Program data =

verify data?

≥ n?

Additional-programming data computation

Wait (tcswe) μs

m = 1

128-byte data

verification completed?

m = 0?

Increment

address

Programming failure

Yes

Wait (tcswe) μs

Clear SWE bit in FLMCR1

≥ (N)?

Reprogram Data

(X')

Verify Data

(V)

Additional-Programming

Data (Y)

Comments

Additional programming to be executed

Additional programming not to be executed

Successively write 128-byte reprogram

data area in RAM to flash memory

Write Pulse (Write pulse)

RAM

Program data storage

area (128 bytes)

Reprogram data storage

area (128 bytes)

Additional-programming data

storage area (128 bytes)

Store 128 bytes of program data in program

data area and reprogram data area

Programming Count (n)

998

999

1000

Programming Time (z)

μs

tsp30

tsp200

Original Data

(D)

Verify Data

(V)

Reprogram Data

(X)

Comments

Programming completed

Programming incomplete:

reprogramming to be executed

Reprogram Data Computation Table

—

Still in erased state: no action

Additional-Programming Data Computation Table

Transfer additional-programming data

to additional-programming data area

Reprogram data computation

Clear PV bit in FLMCR1

Wait (tcpv) μs

Transfer reprogram data to reprogram

data area

Successively write 128-byte data from

additional-programming data area

in RAM to flash memory

← n + 1

Note: Use a 10

μs write pulse for additional programming.

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of

the first address written to must be H'00 or H'80. A 128-byte data

transfer must be performed even if writing fewer than 128 bytes;

in this case, H'FF data must be written to the extra addresses.

2. Verify data is read in 16-bit (word) units.

3. Reprogram data is determined by the operation shown in the

table below (comparing the data stored in the program data area

with the verify data). For reprogram data 0 bits, programming is

executed in the next reprogramming loop. Therefore, even bits

for which programming has been completed in the 128-byte

programming loop will be subject to programming again if they

fail the subsequent verify operation.

4. A 128-byte area for storing program data, a 128-byte area for

storing reprogram data, and a 128-byte area for storing

additional-programming data must be provided in RAM. The

reprogram and additional-programming data contents are

modified as programming proceeds.

5. A write pulse of 30

μs or 200 μs is applied according to the

progress of the programming operation. See Note 6 for details of

the pulse widths. When writing of additional-programming data is

executed, a 10

μs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.

7. The wait times and the value of N are shown in table 18.15, Flash Memory Characteristics.

Programming must be executed

in the erased state. Do not

perform additional programming

on addresses that have already

been programmed.

Reprogram

Figure 15.11 H8/3022F Program/Program-Verify Flowchart

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