H8SLASH3021 datasheet(504/712 Pages) RENESAS

504 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 480 of 684

REJ09B0352-0200

End of erasing

Start

Set SWE bit in FLMCR1

Set ESU bit in FLMCR1

Set E bit in FLMCR1

Wait (tsswe)

μs

Wait (tsesu)

μs

n = 1

Set EBR1 or EBR2

Enable WDT

Wait (tse) ms

Wait (tce)

μs

Wait (tcesu)

μs

Wait (tsev)

μs

Set block start address to verify address

Wait (tsevr)

μs

Wait (tcev)

μs

Start erase

Clear E bit in FLMCR1

Clear ESU bit in FLMCR1

Set EV bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV bit in FLMCR1

Wait (tcev)

μs

Clear EV bit in FLMCR1

Clear SWE bit in FLMCR1

Disable WDT

Halt erase

Verify data = all "1"?

Last address of block?

End of

erasing of all erase

blocks?

Erase failure

Clear SWE bit in FLMCR1

≥ (N)?

Yes

← n + 1

Increment

address

Wait (tcswez)

μs

Wait (tcswe)

μs

Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.

2. Verify data is read in 16-bit (word) units.

3. Set only one bit in the erase block register (EBR1/EBR2). More than one bit must not be set.

4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.

5. The wait times and the value of N are shown in table 18.15, Flash Memory Characteristics.

Erasing must be performed

in block units.

Re-erase

Figure 15.12 H8/3022F Erase/Erase-Verify Flowchart

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