H8SLASH3021 datasheet(506/712 Pages) RENESAS

506 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 482 of 684

REJ09B0352-0200

Table 15.11 Hardware Protection

Functions

Item

Description

Program Erase

Verify*

FWE pin

protection

• When a low level is input to the FWE pin,

FLMCR1, EBR1, and EBR2 are initialized,

and the program/erase-protected state is

entered. *

No*

Reset/standby

protection

• In a power-on reset (including a WDT power-

on reset) and in standby mode, FLMCR1,

FLMCR2, EBR1, and EBR2 are initialized,

and the program/erase-protected state is

entered.

• In a reset via the

RES pin, the reset state is

not entered unless the

RES pin is held low

until oscillation stabilizes after powering on.

In the case of a reset during operation, hold

the

RES pin low for the RES pulse width

specified in the AC Characteristics section. *

No*

Error protection

• When a microcomputer operation error (error

generation (FLER=1)) was detected while

flash memory was being

programmed/erased, error protection is

enabled. At this time, the FLMCR and EBR

settings are held, but programming/erasing is

aborted at the time the error was generated.

Error protection is released only by a reset

via the

RES pin or a WDT reset, or in the

hardware standby mode.

No*

Yes*

Notes: 1. Two modes: program-verify and erase-verify.

2. Excluding a RAM area overlapping flash memory.

3. All blocks are unerasable and block-by-block specification is not possible.

4. For details see section 15.11, Notes on Flash Memory Programming and Erasing.

5. See section 4.2.2, Reset Sequence, and section 15.11, Notes on Flash Memory

Programming and Erasing. The H8/3022F requires a minimum of 20 system clock

cycles for a reset during operation.

6. It is possible to perform a program-verify operation on the 128 bytes being

programmed, or an erase-verify operation on the block being erased.

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