H8SLASH3021 datasheet(509/712 Pages) RENESAS

509 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 485 of 684

REJ09B0352-0200

Figure 15.13 shows the flash memory state transition diagram.

RD VF PR ER FLER= 0

Error

occurrence

P= 1 or E= 1

P= 0

E= 0

Error

occurre

nce

(software

standby)

Reset or hardware standby

Reset

hardwar

e standby

or software

stan

dby

Reset

lease

and

hardw

are

standby

release

and

software

standby

release

Reset or hardware standby

Reset

hardware

standby

RD VF PR ER INIT FLER= 0

Program mode

Erase mode

RD VF

PR ER FLER= 0

Memory read

verify mode

Reset or standby

(hardware protection)

RD VF

PR ER FLER= 1

RD VF PR ER INIT FLER= 1

Error protection mode

(software standby)

Software standby mode

Software standby

mode release

RD: Memory read possible

VF:

Verify-read possible

PR:

Programming possible

ER:

Erasing possible

RD: Memory read not possible

VF: Verify-read not possible

PR: Programming not possible

ER: Erasing not possible

INIT: Register (FLMCR, EBR) initialization state

Legend

Figure 15.13 Flash Memory State Transitions

(Modes 5, 6, and 7 (on-chip ROM enabled), high level applied to FWE pin)

The error protection function is invalid for abnormal operations other than the FLER bit setting

conditions. Also, if a certain time has elapsed before this protection state is entered, damage may

already have been caused to the flash memory. Consequently, this function cannot provide

complete protection against damage to flash memory.

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