H8SLASH3021 datasheet(498/712 Pages) RENESAS

498 / 712 page

15. ROM

Rev.2.00 Mar. 22, 2007 Page 474 of 684

REJ09B0352-0200

in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128

bytes; in this case, H'FF data must be written to the extra addresses.

Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.

Set a WDT overflow period greater than (t

spsu + tsp + tcp + tcpsu) µs. After this, preparation for

program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the

elapse of (t

spsu) µs or more, the operating mode is switched to program mode by setting the P bit in

FLMCR1. The time during which the P bit is set is the flash memory programming time. Make a

setting in the program so that the time for one write operation is within the (t

sp) µs range. The wait

time after the P bit is set must be changed according to the degree of progress through the

programming operation. For details see section 15.7.3, Notes on Program/Program-Verify

Procedure.

15.7.2

Program-Verify Mode

In program-verify mode, the data written in program mode is read to check whether it has been

correctly written in the flash memory.

After the elapse of a given programming time, the programming mode is exited (the P bit in

FLMCR1 is cleared, then the PSU bit is cleared at least (t

cp) µs later). The watchdog timer is

cleared, and the operating mode is switched to program-verify mode by setting the PV bit in

FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data should be made to

the addresses to be read. The dummy write should be executed after the elapse of (t

spv) µs or more.

When the flash memory is read in this state (verify data is read in 16-bit units), the data at the

latched address is read. Wait at least (t

spvr) µs after the dummy write before performing this read

operation. Next, the written data is compared with the verify data, and reprogram data is computed

(see figure 15.11) and transferred to the reprogram data area. After 128 bytes of data have been

verified, exit program-verify mode, wait for at least (t

cpv) µs, then clear the SWE bit in FLMCR1. If

reprogramming is necessary, set program mode again, and repeat the program/program-verify

sequence as before. However, ensure that the program/program-verify sequence is not repeated

more than (N) times on the same bits.

Leave a wait time of at least (t

cswe) µs after clearing SWE.

15.7.3

Notes on Program/Program-Verify Procedure

1. The program/program-verify procedure for the H8/3022F is a 128-byte-unit programming

algorithm.

Note that the algorithm is different from that of the H8/3039F-ZTAT Group (32-byte-unit

programming).

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