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H8/3021 Datasheet(PDF) 531 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 531 Page - Renesas Technology Corp |
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531 / 712 page ![]() 16. Clock Pulse Generator Rev.2.00 Mar. 22, 2007 Page 507 of 684 REJ09B0352-0200 Table 16.4 and Figure 16.7 show the timing for the external clock output stabilization delay time. The oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (t DEXT). As clock signal output is not confirmed during the tDEXT period, the reset signal should be driven low and the reset state maintained during this time. Table 16.4 External Clock Output Stabilization Delay Time Conditions: V CC = 3.0 V to 3.6 V, AVCC = 3.3 V to 5.5 V, VSS = AVSS = 0 V Item Symbol Min Max Unit Notes External clock output stabilization delay time t DEXT* 500 — μs Figure 16.7 Note: * t DEXT includes a 10 tcyc RES pulse width (tRESW). VCC STBY EXTAL φ RES tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW). 2.7 V VIH Figure 16.7 External Clock Output Stabilization Delay Time |
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