H8SLASH3021 datasheet(532/712 Pages) RENESAS

532 / 712 page

16. Clock Pulse Generator

Rev.2.00 Mar. 22, 2007 Page 508 of 684

REJ09B0352-0200

16.3

Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty

cycle of the clock signal from the oscillator to generate the system clock (

φ).

16.4

Prescalers

The prescalers divide the system clock (

φ) to generate internal clocks (φ/2 to φ/4096).

16.5

Frequency Divider

The frequency divider divides the duty-adjusted clock signal to generate the system clock (

φ). The

frequency division ratio can be changed dynamically by modifying the value in DIVCR, as

described below. Power consumption in the chip is reduced in almost direct proportion to the

frequency division ratio. The system clock generated by the frequency divider can be output at the

φ pin.

16.5.1

Table 16.5 summarizes the frequency division register.

Table 16.5

Frequency Division Register

Address*

Name

Abbreviation

R/W

Initial Value

H'FF5D

Division control register

DIVCR

R/W

H'FC

Note:

The lower 16 bits of the address are shown.

16.5.2

Division Control Register (DIVCR)

DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency

divider.

Bit

Initial value

Read/Write

—

DIV0

R/W

—

DIV1

R/W

Reserved bits

Divide bits 1 and 0

These bits select the

frequency division ratio

H8/3021 Datasheet(PDF) 532 Page - Renesas Technology Corp

H8/3021 Datasheet(HTML) 532 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL