H8SLASH3021 datasheet(533/712 Pages) RENESAS

533 / 712 page

16. Clock Pulse Generator

Rev.2.00 Mar. 22, 2007 Page 509 of 684

REJ09B0352-0200

DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.

Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as

follows.

Bit 1

DIV1

Bit 0

DIV0

Frequency Division Ratio

1/1

(Initial value)

1/2

1/4

1/8

16.5.3

Usage Notes

The DIVCR setting changes the

φ frequency, so note the following points.

• Select a frequency division ratio that stays within the assured operation range specified for the

clock cycle time t

cyc in the AC electrical characteristics. Note that φMIN = 1 MHz. Avoid settings

that give system clock frequencies less than 1 MHz.

• All on-chip module operations are based on φ. Note that the timing of timer operations, serial

communication, and other time-dependent processing differs before and after any change in

the division ratio. The waiting time for exit from software standby mode also changes when

the division ratio is changed. For details, see section 17.4.3, Selection of Oscillator Waiting

Time After Exit from Software Standby Mode.

H8/3021 Datasheet(PDF) 533 Page - Renesas Technology Corp