H8SLASH3021 datasheet(537/712 Pages) RENESAS

537 / 712 page

17. Power-Down State

Rev.2.00 Mar. 22, 2007 Page 513 of 684

REJ09B0352-0200

17.2

This LSI has a system control register (SYSCR) that controls the power-down state, and a module

standby control register (MSTCR) that controls the module standby function. Table 17.2

summarizes this register.

Table 17.2

Address*

Name

Abbreviation

R/W

Initial Value

H'FFF2

System control register

SYSCR

R/W

H'0B

H'FF5E

Module standby control

MSTCR

R/W

H'40

Note:

Lower 16 bits of the address.

17.2.1

System Control Register (SYSCR)

Bit

Initial value

Read/Write

SSBY

R/W

STS2

R/W

STS1

R/W

STS0

R/W

RAME

R/W

NMIEG

R/W

—

Software standby

Enables transition to

software standby mode

RAM enable

Standby timer select 2 to 0

These bits select the

waiting time at exit from

software standby mode

User bit enable

NMI edge select

Reserved bit

SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) control

the power-down state. For information on the other SYSCR bits, see section 3.3, System Control

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