H8SLASH3021 datasheet(538/712 Pages) RENESAS

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17. Power-Down State

Rev.2.00 Mar. 22, 2007 Page 514 of 684

REJ09B0352-0200

Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software

standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal

operation. To clear this bit, write 0.

Bit 7

SSBY

Description

SLEEP instruction causes transition to sleep mode

(Initial value)

SLEEP instruction causes transition to software standby mode

Note:

Clear the SWE bit before executing the SLEEP instruction.

Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU

and on-chip supporting modules wait for the clock to settle when software standby mode is exited

by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to

the clock frequency so that the waiting time (for the clock to stabilize) will be at least 7 ms. See

table 17.3. If an external clock is used, any setting is permitted.

Bit 6

STS2

Bit 5

STS1

Bit 4

STS0

Description

Waiting time = 8192 states

(Initial value)

Waiting time = 16384 states

Waiting time = 32768 states

Waiting time = 65536 states

Waiting time = 131072 states

Waiting time = 1024 states

—

Illegal setting

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