H8SLASH3021 datasheet(542/712 Pages) RENESAS

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17. Power-Down State

Rev.2.00 Mar. 22, 2007 Page 518 of 684

REJ09B0352-0200

17.4

Software Standby Mode

17.4.1

Transition to Software Standby Mode

To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in

SYSCR.

In software standby mode, current dissipation is reduced to an extremely low level because the

CPU, clock, and on-chip supporting modules all halt. The on-chip supporting modules are reset

and halted. As long as the specified voltage is supplied, however, CPU register contents and on-

chip RAM data are retained. The settings of the I/O ports are also held.

17.4.2

Exit from Software Standby Mode

Software standby mode can be exited by input of an external interrupt at the NMI,

IRQ

0, IRQ1, or

by input at the

RES or STBY pin.

Exit by Interrupt: When an NMI, IRQ

0, or IRQ1 interrupt request signal is received, the clock

oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0 in

SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and

interrupt exception handling begins. Software standby mode is not exited if the interrupt enable

bits of interrupts IRQ

0, and IRQ1 are cleared to 0, or if these interrupts are masked in the CPU.

Exit by

RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are

supplied immediately to the entire chip. The

RES signal must be held low long enough for the

clock oscillator to stabilize. When

RES goes high, the CPU starts reset exception handling.

Exit by

STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.

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