H8SLASH3021 datasheet(539/712 Pages) RENESAS

539 / 712 page

17. Power-Down State

Rev.2.00 Mar. 22, 2007 Page 515 of 684

REJ09B0352-0200

17.2.2

Module Standby Control Register (MSTCR)

MSTCR is an 8-bit readable/writable register that controls output of the system clock (

φ). It also

controls the module standby function, which places individual on-chip supporting modules in the

standby state. Module standby can be designated for the ITU, SCI0, SCI1, and A/D converter

modules.

Bit

Initial value

Read/Write

PSTOP

R/W

—

MSTOP5

R/W

MSTOP4

R/W

MSTOP3

R/W

MSTOP0

R/W

—

φ clock stop

Enables or disables

output of the system clock

Module standby 5 to 3, and 0

These bits select modules

to be placed in standby

Reserved bit

MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—

φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).

Bit 7

PSTOP

Description

System clock output is enabled

(Initial value)

System clock output is disabled

Bit 6—Reserved: This bit cannot be modified and is always read as 1.

Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.

Bit 5

MSTOP5

Description

ITU operates normally

(Initial value)

ITU is in standby state

H8/3021 Datasheet(PDF) 539 Page - Renesas Technology Corp

H8/3021 Datasheet(HTML) 539 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL