H8SLASH3021 datasheet(133/712 Pages) RENESAS

133 / 712 page

6. Bus Controller

Rev.2.00 Mar. 22, 2007 Page 109 of 684

REJ09B0352-0200

6.1.3

Pin Configuration

Table 6.1 summarizes the bus controller’s input/output pins.

Table 6.1

Bus Controller Pins

Name

Abbreviation

I/O

Function

Address strobe

Output

Strobe signal indicating valid address output on

the address bus

Read

Output

Strobe signal indicating reading from the

external address space

Write

Output

Strobe signal indicating writing to the external

address space, with valid data on the data

bus(D

7 to D0)

Wait

WAIT

Input

Wait request signal for access to external three-

state-access areas

6.1.4

Table 6.2 summarizes the bus controller’s registers.

Table 6.2

Bus Controller Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'FFED

Access state control register

ASTCR

R/W

H'FF

H'FFEE

Wait control register

WCR

R/W

H'F3

H'FFEF

Wait state controller enable register

WCER

R/W

H'FF

H'FFF3

Address control register

ADRCR

R/W

H'FE

Note:

Lower 16 bits of the address.

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