H8SLASH3021 datasheet(137/712 Pages) RENESAS

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6. Bus Controller

Rev.2.00 Mar. 22, 2007 Page 113 of 684

REJ09B0352-0200

6.2.4

Address Control Register (ADRCR)

ADRCR is an 8-bit readable/writable register that enables address output on bus lines A

23 to A21.

Bit

Initial value

Read/Write

Initial value

Read/Write

A23E

—

R/W

A22E

—

R/W

A21E

—

R/W

—

R/W

—

Address 23 to 21 enable

These bits enable PA6 to

PA4 to be used for A23 to

A21 address output

Reserved bits

Modes

1 and 5 to 7

Mode 3

ADRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Address 23 Enable (A

23E): Enables PA4 to be used as the A23 address output pin. Writing 0

in this bit enables A

23 address output from PA4. In modes other than 3 and 6 this bit cannot be

modified and PA

4 has its ordinary input/output functions

Bit 7

23E

Description

PA4 is the A

23 address output pin

PA4 is the PA

4/TP4/TIOCA1 input/output pin

(Initial value)

Bit 6—Address 22 Enable (A

22E): Enables PA5 to be used as the A22 address output pin. Writing 0

in this bit enables A

22 address output from PA5. In modes other than 3 and 6 this bit cannot be

modified and PA

5 has its ordinary input/output functions.

Bit 6

22E

Description

5 is the A22 address output pin

5 is the PA5/TP5/TIOCB1 input/output pin

(Initial value)

H8/3021 Datasheet(PDF) 137 Page - Renesas Technology Corp

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