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H8/3021 Datasheet(PDF) 215 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 215 Page - Renesas Technology Corp |
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215 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 191 of 684 REJ09B0352-0200 Block Diagrams of Channels 3 and 4: Figure 8.4 is a block diagram of channel 3. Figure 8.5 is a block diagram of channel 4. Legend TCNT3: GRA3, GRB3: BRA3, BRB3: TCR3: TIOR3: TIER3: TSR3: Timer counter 3 (16 bits) General registers A3 and B3 (input capture/output compare registers) (16 bits 2) Buffer registers A3 and B3 (input capture/output compare buffer registers) (16 bits 2) Timer control register 3 (8 bits) Clock selector Comparator Control logic TCLKA to TCLKD φ, φ/2, φ/4, φ/8 TIOCA3 TIOCB3 Module data bus × IMIA3 IMIB3 OVI3 Timer I/O control register 3 (8 bits) Timer interrupt enable register 3 (8 bits) Timer status register 3 (8 bits) × Figure 8.4 Block Diagram of Channel 3 |
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