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H8/3021 Datasheet(PDF) 213 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 213 Page - Renesas Technology Corp |
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213 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 189 of 684 REJ09B0352-0200 Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 8.2. Clock selector Comparator Control logic TCLKA to TCLKD φ, φ/2, φ/4, φ/8 TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0 Module data bus Legend TCNT: GRA, GRB: TCR: TIOR: TIER: TSR: Timer counter (16 bits) General registers A and B (input capture/output compare registers) (16 bits 2) Timer control register (8 bits) Timer I/O control register (8 bits) Timer interrupt enable register (8 bits) Timer status register (8 bits) × Figure 8.2 Block Diagram of Channels 0 and 1 (for Channel 0) |
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