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H8/3021 Datasheet(PDF) 212 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 212 Page - Renesas Technology Corp |
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212 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 188 of 684 REJ09B0352-0200 8.1.2 Block Diagrams ITU Block Diagram (overall): Figure 8.1 is a block diagram of the ITU. Module data bus IMIA0 to IMIA4 IMIB0 to IMIB4 OVI0 to OVI4 TCLKA to TCLKD φ, φ/2, φ/4, φ/8 TOCXA4, TOCXB4 Clock selector Control logic TIOCA0 to TIOCA4 TIOCB0 to TIOCB4 TOER TOCR TSTR TSNC TMDR TFCR TOER: TOCR: TSTR: TSNC: TMDR: TFCR: Legend Timer output master enable register (8 bits) Timer output control register (8 bits) Timer start register (8 bits) Timer synchro register (8 bits) Timer mode register (8 bits) Timer function control register (8 bits) Figure 8.1 ITU Block Diagram (Overall) |
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