H8SLASH3021 datasheet(226/712 Pages) RENESAS

226 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 202 of 684

REJ09B0352-0200

8.2.3

Timer Mode Register (TMDR)

TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also

selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.

Bit

Initial value

Read/Write

—

MDF

R/W

FDIR

R/W

PWM4

R/W

PWM3

R/W

PWM0

R/W

PWM2

R/W

PWM1

R/W

Reserved bit

PWM mode 4 to 0

These bits select PWM

mode for channels 4 to 0

Phase counting mode flag

Selects phase counting mode for channel 2

Flag direction

Selects the setting condition for the overflow

flag (OVF) in timer status register 2 (TSR2)

TMDR is initialized to H'80 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in

phase counting mode.

Bit 6

MDF

Description

Channel 2 operates normally

(Initial value)

Channel 2 operates in phase counting mode

When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an

up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts

both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows.

H8/3021 Datasheet(PDF) 226 Page - Renesas Technology Corp

H8/3021 Datasheet(HTML) 226 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL