H8SLASH3021 datasheet(230/712 Pages) RENESAS

230 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 206 of 684

REJ09B0352-0200

Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.

Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels

3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode.

Bit 5

CMD1

Bit 4

CMD0

Description

Channels 3 and 4 operate normally

(Initial value)

Channels 3 and 4 operate together in complementary PWM mode

Channels 3 and 4 operate together in reset-synchronized PWM mode

Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer

counter or counters that will be used in these modes.

When these bits select complementary PWM mode or reset-synchronized PWM mode, they take

precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of

timer sync bits SYNC4 and SYNC3 in the timer synchro register (TSNC) are valid in

complementary PWM mode and reset-synchronized PWM mode, however. When complementary

PWM mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and

SYNC4 both to 1 in TSNC).

Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or

whether GRB4 is buffered by BRB4.

Bit 3

BFB4

Description

GRB4 operates normally

(Initial value)

GRB4 is buffered by BRB4

Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or

whether GRA4 is buffered by BRA4.

Bit 2

BFA4

Description

GRA4 operates normally

(Initial value)

GRA4 is buffered by BRA4

H8/3021 Datasheet(PDF) 230 Page - Renesas Technology Corp