H8SLASH3021 datasheet(232/712 Pages) RENESAS

232 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 208 of 684

REJ09B0352-0200

Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.

Bit 5—Master Enable TOCXB

4 (EXB4): Enables or disables ITU output at pin TOCXB4.

Bit 5

EXB4

Description

TOCXB

4 output is disabled regardless of TFCR settings (TOCXB4 operates as a

generic input/output pin). If XTGD = 0, EXB4 is cleared to 0 when input capture A

occurs in channel 1.

TOCXB

4 is enabled for output according to TFCR settings

(Initial value)

Bit 4—Master Enable TOCXA

4 (EXA4): Enables or disables ITU output at pin TOCXA4.

Bit 4

EXA4

Description

TOCXA

4 output is disabled regardless of TFCR settings (TOCXA4 operates as a

generic input/output pin).

If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.

TOCXA

4 is enabled for output according to TFCR settings

(Initial value)

Bit 3—Master Enable TIOCB

3 (EB3): Enables or disables ITU output at pin TIOCB3.

Bit 3

EB3

Description

TIOCB

3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3 operates

as a generic input/output pin).

If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.

TIOCB

3 is enabled for output according to TIOR3 and TFCR settings

(Initial value)

Bit 2—Master Enable TIOCB

4 (EB4): Enables or disables ITU output at pin TIOCB4.

Bit 2

EB4

Description

TIOCB

4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4 operates

as a generic input/output pin).

If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.

TIOCB

4 is enabled for output according to TIOR4 and TFCR settings

(Initial value)

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