H8SLASH3021 datasheet(234/712 Pages) RENESAS

234 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 210 of 684

REJ09B0352-0200

8.2.6

Timer Output Control Register (TOCR)

TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in

complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.

Bit

Initial value

Read/Write

—

XTGD

R/W

—

OLS3

R/W

—1

—

OLS4

R/W

Reserved bits

Output level select 3, 4

These bits select output

levels in complementary

PWM mode and reset-

synchronized PWM mode

External trigger disable

Selects externally triggered disabling of output in

complementary PWM mode and reset-synchronized

PWM mode

Reserved bits

The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode

and reset-synchronized PWM mode. These settings do not affect other modes.

TOCR is initialized to H'FF by a reset and in standby mode.

Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.

Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output

in complementary PWM mode and reset-synchronized PWM mode.

Bit 4

XTGD

Description

Input capture A in channel 1 is used as an external trigger signal in complementary

PWM mode and reset-synchronized PWM mode.

When an external trigger occurs, bits 5 to 0 in the timer output master enable register

(TOER) are cleared to 0, disabling ITU output.

External triggering is disabled

(Initial value)

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