H8SLASH3021 datasheet(237/712 Pages) RENESAS

237 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 213 of 684

REJ09B0352-0200

When a general register is used as an output compare register, its value is constantly compared

with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set

to 1 in the timer status register (TSR). Compare match output can be selected in TIOR.

When a general register is used as an input capture register, rising edges, falling edges, or both

edges of an external input capture signal are detected and the current TCNT value is stored in the

general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The

valid edge or edges of the input capture signal are selected in TIOR.

TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized

PWM mode.

General registers are linked to the CPU by an internal 16-bit bus and can be written or read by

either word access or byte access.

General registers are initialized to the output compare function (with no output signal) by a reset

and in standby mode. The initial value is H'FFFF.

8.2.9

Buffer Registers (BRA, BRB)

The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3

and 4.

Channel

Abbreviation

Function

BRA3, BRB3

Used for buffering

• When the corresponding GRA or GRB functions as an output

compare register, BRA or BRB can function as an output

compare buffer register: the BRA or BRB value is

automatically transferred to GRA or GRB at compare match

BRA4, BRB4

• When the corresponding GRA or GRB functions as an input

capture register, BRA or BRB can function as an input capture

buffer register: the GRA or GRB value is automatically

transferred to BRA or BRB at input capture

Bit

Initial value

Read/Write

R/W

H8/3021 Datasheet(PDF) 237 Page - Renesas Technology Corp