H8SLASH3021 datasheet(238/712 Pages) RENESAS

238 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 214 of 684

REJ09B0352-0200

A buffer register is a 16-bit readable/writable register that is used when buffering is selected.

Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.

The buffer register and general register operate as a pair. When the general register functions as an

output compare register, the buffer register functions as an output compare buffer register. When

the general register functions as an input capture register, the buffer register functions as an input

capture buffer register.

The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by

either word or byte access.

Buffer registers are initialized to H'FFFF by a reset and in standby mode.

8.2.10

Timer Control Registers (TCR)

TCR is an 8-bit register. The ITU has five TCRs, one in each channel.

Channel

Abbreviation

Function

TCR0

TCR controls the timer counter. The TCRs in all channels are

TCR1

functionally identical. When phase counting mode is selected in

TCR2

channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to

TCR3

TPSC0 in TCR2 are ignored.

TCR4

Bit

Initial value

Read/Write

—

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Timer prescaler 2 to 0

These bits select the

counter clock

Reserved bit

Clock edge 1/0

These bits select external clock edges

Counter clear 1/0

These bits select the counter clear source

H8/3021 Datasheet(PDF) 238 Page - Renesas Technology Corp

H8/3021 Datasheet(HTML) 238 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL