H8SLASH3021 datasheet(239/712 Pages) RENESAS

239 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 215 of 684

REJ09B0352-0200

Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects

the edge or edges of external clock sources, and selects how the counter is cleared.

TCR is initialized to H'80 by a reset and in standby mode.

Bit 7—Reserved: This bit cannot be modified and is always read as 1.

Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.

Bit 6

CCLR1

Bit 5

CCLR0

Description

TCNT is not cleared

(Initial value)

TCNT is cleared by GRA compare match or input capture*

TCNT is cleared by GRB compare match or input capture*

Synchronous clear: TCNT is cleared in synchronization

with other synchronized timers*

Notes: 1. TCNT is cleared by compare match when the general register functions as an output

compare match register, and by input capture when the general register functions as an

input capture register.

2. Selected in the timer synchro register (TSNC).

Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges

when an external clock source is used.

Bit 4

CKEG1

Bit 3

CKEG0

Description

Count rising edges

(Initial value)

Count falling edges

—

Count both edges

When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.

Phase counting takes precedence.

H8/3021 Datasheet(PDF) 239 Page - Renesas Technology Corp