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H8/3021 Datasheet(PDF) 243 Page - Renesas Technology Corp

Part # H8/3021
Description  16-Bit Single-Chip Microcomputer
PDF  712 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/3021 Datasheet(HTML) 243 Page - Renesas Technology Corp

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8. 16-Bit Integrated Timer Unit (ITU)
Rev.2.00 Mar. 22, 2007 Page 219 of 684
REJ09B0352-0200
8.2.12
Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel
Abbreviation
Function
0
TSR0
Indicates input capture, compare match, and overflow status
1
TSR1
2
TSR2
3
TSR3
4
TSR4
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
*
2
OVF
0
R/(W)
Reserved bits
Note: * Only 0 can be written to clear the flag.
*
1
IMFB
0
R/(W)
*
0
IMFA
0
R/(W)
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register
(TIER).
TSR is initialized to H'F8 by a reset and in standby mode.



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