H8SLASH3021 datasheet(244/712 Pages) RENESAS

244 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 220 of 684

REJ09B0352-0200

Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.

Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.

Bit 2

OVF

Description

[Clearing condition]

Read OVF when OVF = 1, then write 0 in OVF

(Initial value)

[Setting condition]

TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF*

Notes: *

TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow

occurs only under the following conditions:

1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)

2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0

in TFCR)

Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB

compare match or input capture events.

Bit 1

IMFB

Description

[Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB

(Initial value)

[Setting conditions]

TCNT = GRB when GRB functions as a compare match register.

TCNT value is transferred to GRB by an input capture signal, when GRB functions as

an input capture register.

Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA

compare match or input capture events.

Bit 0

IMFA

Description

[Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA.

(Initial value)

[Setting conditions]

TCNT = GRA when GRA functions as a compare match register.

TCNT value is transferred to GRA by an input capture signal, when GRA functions as

an input capture register.

H8/3021 Datasheet(PDF) 244 Page - Renesas Technology Corp