H8SLASH3021 datasheet(231/712 Pages) RENESAS

231 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 207 of 684

REJ09B0352-0200

Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or

whether GRB3 is buffered by BRB3.

Bit 1

BFB3

Description

GRB3 operates normally

(Initial value)

GRB3 is buffered by BRB3

Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or

whether GRA3 is buffered by BRA3.

Bit 0

BFA3

Description

GRA3 operates normally

(Initial value)

GRA3 is buffered by BRA3

8.2.5

Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3

and 4.

Bit

Initial value

Read/Write

—

EXB4

R/W

EXA4

R/W

EB3

R/W

EA3

R/W

EB4

R/W

EA4

R/W

Reserved bits

Master enable TOCXA4, TOCXB4

These bits enable or disable output

settings for pins TOCXA4 and TOCXB4

Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4

These bits enable or disable output settings for pins

TIOCA3, TIOCB3 , TIOCA4, and TIOCB4

TOER is initialized to H'FF by a reset and in standby mode.

H8/3021 Datasheet(PDF) 231 Page - Renesas Technology Corp

H8/3021 Datasheet(HTML) 231 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL