H8SLASH3021 datasheet(276/712 Pages) RENESAS

276 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 252 of 684

REJ09B0352-0200

TCNT4

OVF

Buffer transfer

signal (BR to GR)

H'0001

H'0000

H'FFFF

H'0000

Set to 1

Flag not set

No buffer transfer

Buffer transfer

Underflow

Overflow

Figure 8.38 Undershoot Timing

In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when

an underflow occurs. When buffering is selected, buffer register contents are transferred to the

general register at compare match A3 during up-counting, and when TCNT4 underflows.

General Register Settings in Complementary PWM Mode: When setting up general registers

for complementary PWM mode or changing their settings during operation, note the following

points.

• Initial settings

Do not set values from H'0000 to T – 1 (where T is the initial value of TCNT3). After the

counters start and the first compare match A3 event has occurred, however, settings in this

range also become possible.

• Changing settings

Use the buffer registers. Correct waveform output may not be obtained if a general register is

written to directly.

• Cautions on changes of general register settings

Figure 8.39 shows six correct examples and one incorrect example.

H8/3021 Datasheet(PDF) 276 Page - Renesas Technology Corp