H8SLASH3021 datasheet(280/712 Pages) RENESAS

280 / 712 page

8. 16-Bit Integrated Timer Unit (ITU)

Rev.2.00 Mar. 22, 2007 Page 256 of 684

REJ09B0352-0200

8.4.7

Phase Counting Mode

In phase counting mode the phase difference between two external clock inputs (at the TCLKA

and TCLKB pins) is detected, and TCNT2 counts up or down accordingly.

In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock

input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to

TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in

TIOR2, TIER2, TSR2, GRA2, and GRB2 are valid. The input capture and output compare

functions can be used, and interrupts can be generated.

Phase counting is available only in channel 2.

Sample Setup Procedure for Phase Counting Mode: Figure 8.43 shows a sample procedure for

setting up phase counting mode.

Phase counting mode

Select phase counting mode

Select flag setting condition

Start counter

Phase counting mode

Set the MDF bit in TMDR to 1 to select

phase counting mode.

Select the flag setting condition with

the FDIR bit in TMDR.

Set the STR2 bit to 1 in TSTR to start

the timer counter.

Figure 8.43 Setup Procedure for Phase Counting Mode (Example)

H8/3021 Datasheet(PDF) 280 Page - Renesas Technology Corp