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H8/3021 Datasheet(PDF) 284 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 284 Page - Renesas Technology Corp |
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284 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 260 of 684 REJ09B0352-0200 Examples of Buffering: Figure 8.49 shows an example in which GRA is set to function as an output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA. This operation is repeated each time compare match A occurs. Figure 8.50 shows the transfer timing. GRB H'0250 H'0200 H'0100 H'0000 BRA GRA TIOCB TIOCA TCNT value Counter cleared by compare match B Time Toggle output Toggle output Compare match A H'0200 H'0250 H'0100 H'0200 H'0100 H'0200 H'0200 Figure 8.49 Register Buffering (Example 1: Buffering of Output Compare Register) |
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