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H8/3021 Datasheet(PDF) 286 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 286 Page - Renesas Technology Corp |
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286 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 262 of 684 REJ09B0352-0200 Figure 8.51 shows an example in which GRA is set to function as an input capture register buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous GRA value is simultaneously transferred to BRA. Figure 8.52 shows the transfer timing. H'0180 H'0160 H'0005 H'0000 TIOCB TIOCA GRA BRA GRB H'0005 H'0160 H'0005 H'0180 TCNT value Counter cleared by input capture B Time Input capture A H'0160 Figure 8.51 Register Buffering (Example 2: Buffering of Input Capture Register) |
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