| Electronic Components Datasheet Search |
|
H8/3021 Datasheet(PDF) 290 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
H8/3021 Datasheet(HTML) 290 Page - Renesas Technology Corp |
|
290 / 712 page ![]() 8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 266 of 684 REJ09B0352-0200 Timing of Disabling of ITU Output by External Trigger: If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output. Figure 8.55 shows the timing. φ TIOCA1 pin TOER ITU output I/O port ITU output I/O port Generic input/output Generic input/output ITU output ITU output Input capture signal ITU output pins NN H'C0 H'C0 N: Arbitrary setting (H'C1 to H'FF) Figure 8.55 Timing of Disabling of ITU Output by External Trigger (Example) Timing of Output Inversion by TOCR: The output levels in reset-synchronized PWM mode and complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and OLS3) in TOCR. Figure 8.56 shows the timing. φ Address TOCR ITU output pin TOCR address Inverted T 1 T 2 T 3 Figure 8.56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |