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H8/3021 Datasheet(PDF) 291 Page - Renesas Technology Corp |
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H8/3021 Datasheet(HTML) 291 Page - Renesas Technology Corp |
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291 / 712 page  8. 16-Bit Integrated Timer Unit (ITU) Rev.2.00 Mar. 22, 2007 Page 267 of 684 REJ09B0352-0200 8.5 Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match: IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR). The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a general register, the compare match signal is not generated until the next timer clock input. Figure 8.57 shows the timing of the setting of IMFA and IMFB. φ TCNT GR IMF IMI TCNT input clock Compare match signal N N + 1 N Figure 8.57 Timing of Setting of IMFA and IMFB by Compare Match |
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