7733 datasheet(86/940 Pages) RENESAS

86 / 940 page

7733 Group User's Manual

4–7

INTERRUPTS

4.3 Interrupt control

Fig. 4.3.2 Interrupt control registers’ structures

INT0

, INT1, and INT2/Key input interrupt control registers (addresses 7D16 to 7F16)

b2b1b0

0 0 0: Level 0 (Interrupt is disabled.)

0 0 1: Level 1

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

A-D

/UART2 trans./rece., UART0 and 1 transmission, UART0 and 1 receive, Timers A0 to A4,

Timers B0 to B2 interrupt control registers (addresses 7016 to 7C16)

b7 b6 b5 b4 b3 b2 b1 b0

Bit

Bit name

Functions

At reset

b2b1b0

0 0 0 : Level 0 (Interrupt is disabled.)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

Not implemented.

Interrupt priority level

selection bits

Interrupt request bit

Un-

defined

0: No interrupt request has occurred.

1: Interrupt request has occurred.

0: Interrupt request bit is set to “1” at “H”

level when level sense is selected;

this bit is set to “1” at falling edge

when edge sense is selected.

1: Interrupt request bit is set to “1” at “L”

level when level sense is selected;

this bit is set to “1” at rising edge

when level sense is selected.

b7 b6 b5 b4 b3 b2 b1 b0

Bit

Bit name

Functions

Interrupt priority level

selection bits

Interrupt request bit (Note)

0: No interrupt request has occurred.

1: Interrupt request has occurred.

Polarity selection bit

Level sense/Edge sense

selection bit

0: Edge sense

1: Level sense

At reset

—

Un-

defined

Not implemented.

—

Note: The interrupt request bits of INT0 to INT2/Key input interrupts are ignored when the level sense is selected.

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