7733 datasheet(93/940 Pages) RENESAS

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7733 Group User's Manual

INTERRUPTS

4–14

@ : Interrupt priority level detection time

Interrupt request is generated.

Interrupt request is accepted.

Instruction

INTACK sequence

Instructions in interrupt routine

Interrupt response time

Time

Time from when an interrupt request occurs until the instruction execution which is in

progress at that time is completed.

Time from when execution of an instruction next to begins (Note) until the instruction

execution which is in progress at completion of interrupt priority level detection.

Note : At this time, detection of interrupt priority level begins.

Time required to execute the INTACK sequence (13 cycles of

at the shortest)

4.7 How interrupts are processed (from acceptance of interrupt request

until execution of interrupt routine)

How interrupts are processed from accepting of an interrupt request until execution of the interrupt routine

is described below.

When an interrupt request is accepted, the interrupt request bit which corresponds to the accepted interrupt

is cleared to “0.” And then, execution of an interrupt routine begins at the cycle immediately after the

instruction execution which was in progress at acceptance of the interrupt request is completed. Figure 4.7.1

shows how interrupts are processed from acceptance of an interrupt request until execution of the interrupt

routine. When the instruction execution which was in progress at acceptance of the interrupt request is

completed, the INTACK (Interrupt acknowledge) sequence is executed and the program branches to the

start address of the interrupt routine allocated in addresses 016 to FFFF16. In the INTACK sequence, the

following procedure is automatically performed in this order.

The contents of the program bank register (PG) immediately before the INTACK sequence is pushed onto

the stack.

The contents of the program counter (PC) immediately before the INTACK sequence is pushed onto the

stack.

The contents of the processor status register (PS) immediately before the INTACK sequence is pushed

onto the stack.

The interrupt disable flag (I) is set to “1.”

The interrupt priority level of the accepted interrupt is set to IPL.

The contents of the program bank register (PG) is cleared to “0016” and the contents of the interrupt vector

address is set into the program counter (PC).

The INTACK sequence requires at least 13 cycles of

φ. Figure 4.7.2 shows the INTACK sequence’s timing.

After the INTACK sequence is completed, the instruction execution begins at the start address of an

interrupt routine.

4.7 How interrupts are processed

Fig. 4.7.1 How interrupts are processed from acceptance of interrupt request until execution of

interrupt routine

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