7733 datasheet(89/940 Pages) RENESAS

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7733 Group User's Manual

INTERRUPTS

4–10

4.4 Interrupt priority level

When the interrupt disable flag (I) = “0” (in other words, when interrupts are enabled), if multiple interrupt

requests reside at the same sampling timing, where the presence of an interrupt request is checked, these

requests are accepted in order of priority levels. In this case, an interrupt request which has the highest

priority is accepted first.

For 16 interrupt sources other than software interrupts (the zero division and BRK instruction) and a

watchdog timer interrupt, an arbitrary priority level can be set by specifying the interrupt priority level

selection bits. Note that the priority level for reset (handled as an interrupt which has the highest priority)

or a watchdog timer interrupt is set by hardware. Figure 4.4.1 shows the interrupt priority level set by

hardware.

Note that software interrupts are not affected by the interrupt priority level. When the zero division or BRK

instruction is executed, a program branches to an interrupt routine.

4.4 Interrupt priority level

Fig. 4.4.1 Interrupt priority level set by hardware

Watchdog

timer

interrupt

Reset

Inside of dotted-line, an arbitrary priority level can be set.

High

Low

Interrupt priority level

16 interrupt sources other than software interrupts

and watchdog timer interrupt

7733 Datasheet(PDF) 89 Page - Renesas Technology Corp