7733 datasheet(21/940 Pages) RENESAS

21 / 940 page

7736 Group User’s Manual

Table of contents

xiv

PART 3 7736 Group

CHAPTER 1. OVERVIEW

1.1 Performance overview ........................................................................................................... 1-2

1.2 Pin configuration .................................................................................................................... 1-3

1.3 Pin description ....................................................................................................................... 1-4

1.3.1 Examples of handling unused pins .............................................................................. 1-8

1.4 Block diagram ....................................................................................................................... 1-13

CHAPTER 2. CENTRAL PROCESSING UNIT (CPU)

2.1 Central processing unit ........................................................................................ 2–2 in part 1

2.2 Bus interface unit

External bus mode A ........................................................................................... 2–10 in part 1

External bus mode B ............................................................................................. 2–2 in part 2

2.3 Accessible area

External bus mode A ........................................................................................... 2–16 in part 1

External bus mode B ............................................................................................. 2–5 in part 2

2.4 Memory allocation ................................................................................................ 2–18 in part 1

2.5 Processor modes ................................................................................................................... 2-2

CHAPTER 3. PROGRAMMABLE I/O PORTS

3.1 Programmable I/O ports and Output-only ports ............................................................ 3-2

3.1.1 Port Pi direction register ............................................................................................... 3-3

3.1.2 Port Pi register ............................................................................................................... 3-4

3.2 Port peripheral circuits ........................................................................................................ 3-6

3.3 Pull-up function ..................................................................................................................... 3-8

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3.3.1 Pull-up function for ports P104 to P107 (KI0 to KI3) ................................................ 3-8

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3.3.2 Pull-up function for ports P62 to P64 (INT0 to INT2) ................................................ 3-8

3.4 Internal peripheral devices’ I/O functions (Ports P42, P5 to P8, P90 to P93 and P104 to P107) ..... 3-10

CHAPTER 4. INTERRUPTS

4.1 Overview ................................................................................................................... 4-2 in part 1

4.2 Interrupt sources ..................................................................................................... 4-4 in part 1

4.3 Interrupt control ...................................................................................................... 4-6 in part 1

4.4 Interrupt priority level .......................................................................................... 4-10 in part 1

4.5 Interrupt priority level detection circuit .......................................................... 4-11 in part 1

4.6 Interrupt priority level detection time .............................................................. 4-13 in part 1

4.7 How interrupts are processed (from acceptance of interrupt request

until execution of interrupt routine) ................................................................. 4-14 in part 1

4.8 Return from interrupt routine ............................................................................. 4-17 in part 1

4.9 Multiple interrupts ................................................................................................. 4-17 in part 1

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4.10 External interrupts (INTi interrupt) .................................................................. 4-19 in part 1

4.11 Precautions for interrupts ................................................................................. 4-23 in part 1

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