7733 datasheet(99/940 Pages) RENESAS

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7733 Group User's Manual

INTERRUPTS

4–20

____

4.10 External interrupts (INTi interrupt)

Fig. 4.10.1 Correspondence between port P6 direction register and input pins for external

interrupts

____

Fig. 4.10.2 INT0 to INT2 interrupt control register’s structure

Bit

Pin TB2IN

Pin TB1IN

Pin TB0IN

Pin INT2/Key input

Pin INT1

Pin INT0

Pin TA4IN

Pin TA4OUT

At reset

Functions

Port P6 direction register (address 10 16)

0 : Input mode

1 : Output mode

When using a pin as an input pin

for an external interrupt, clear the

corresponding bit to “0.”

represents that bits 0, 1 and bits 5 to 7 are not used for external interrupts.

Corresponding pin’s name

INT0

, INT1, and INT2/Key input interrupt control registers (addresses 7D16 to 7F16)

b2b1b0

0 0 0: Level 0 (Interrupt is disabled.)

0 0 1: Level 1

0 1 0: Level 2

0 1 1: Level 3

1 0 0: Level 4

1 0 1: Level 5

1 1 0: Level 6

1 1 1: Level 7

0: Interrupt request bit is set to “1” at “H”

level when level sense is selected;

this bit is set to “1” at falling edge

when edge sense is selected.

1: Interrupt request bit is set to “1” at “L”

level when level sense is selected;

this bit is set to “1” at rising edge

when level sense is selected.

b7 b6 b5 b4 b3 b2 b1 b0

Bit

Bit name

Functions

Interrupt priority level

selection bits

Interrupt request bit (Note)

0: No interrupt request has occurred.

1: Interrupt request has occurred.

polarity selection bit

Level sense/Edge sense

selection bit

0: Edge sense

1: Level sense

At reset

Un-

defined

Not implemented.

—

Note: The interrupt request bits of INT0 to INT2/Key input interrupts are ignored when the level sense is selected.

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