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H8/3028F Datasheet(PDF) 823 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 823 Page - Renesas Technology Corp |
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823 / 923 page ![]() Rev. 2.00, 09/03, page 793 of 890 TMDR—Timer Mode Register H'FFF62 16-bit timer (all channels) 7 — 1 — Bit Initial value Read/Write 6 MDF 0 R/W 5 FDIR 0 R/W 4 — 1 — 3 — 1 — 2 PWM2 0 R/W 1 PWM1 0 R/W 0 PWM0 0 R/W 0 1 Channel 0 operates normally (Initial value) Channel 0 operates in PWM mode PWM mode 0 0 1 Channel 1 operates normally (Initial value) Channel 1 operates in PWM mode PWM mode 1 0 1 Channel 2 operates normally (Initial value) Channel 2 operates in PWM mode PWM mode 2 0 1 OVF is set to 1 in TISRC when TCNT2 overflows or underflows (Initial value) OVF is set to 1 in TISRC when TCNT2 overflows Flag direction 0 1 Channel 2 operates normally (Initial value) Channel 2 operates in phase counting mode Phase counting mode flag |
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