H8SLASH3028F datasheet(825/923 Pages) RENESAS

825 / 923 page

Rev. 2.00, 09/03, page 795 of 890

TISRA—Timer Interrupt Status Register A

H'FFF64

16-bit timer (all channels)

—

IMIEA2

R/W

IMIEA1

R/W

IMIEA0

R/W

—

IMFA2

R/(W)

IMFA1

R/(W)

IMFA0

R/(W)

Input capture/compare match flag A0

[Clearing conditions]

(Initial value)

• Read IMFA0 when IMFA0=1, then write 0 in IMFA0

• DMAC activated by IMIA0 interrupt.

[Setting conditions]

• TCNT0=GRA0 when GRA0 functions as an output

compare register.

• TCNT0 value is transferred to GRA0 by an input capture

signal when GRA0 functions as an input capture register.

Input capture/compare match flag A1

[Clearing conditions]

(Initial value)

• Read IMFA1 when IMFA1=1, then write 0 in IMFA1

• DMAC activated by IMIA1 interrupt.

[Setting conditions]

• TCNT1=GRA1 when GRA1 functions as an output

compare register.

• TCNT1 value is transferred to GRA1 by an input capture

signal when GRA1 functions as an input capture register.

Input capture/compare match flag A2

[Clearing conditions]

(Initial value)

• Read IMFA2 when IMFA2=1, then write 0 in IMFA2

• DMAC activated by IMIA2 interrupt.

[Setting conditions]

• TCNT2=GRA2 when GRA2 functions as an output

compare register.

• TCNT2 value is transferred to GRA2 by an input capture

signal when GRA2 functions as an input capture register.

Bit:

Initial value:

Read/Write:

Note:

* Only 0 can be written, to clear the flag.

Input capture/compare match interrupt enable A0

IMIA0 interrupt requested by IMFA0 flag is disabled

(Initial value)

IMIA0 interrupt requested by IMFA0 is enabled

Input capture/compare match interrupt enable A1

IMIA1 interrupt requested by IMFA1 flag is disabled

(Initial value)

IMIA1 interrupt requested by IMFA1 is enabled

Input capture/compare match interrupt enable A2

IMIA2 interrupt requested by IMFA2 flag is disabled

(Initial value)

IMIA2 interrupt requested by IMFA2 is enabled

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