H8SLASH3028F datasheet(826/923 Pages) RENESAS

826 / 923 page

Rev. 2.00, 09/03, page 796 of 890

TISRB—Timer Interrupt Status Register B

H'FFF65

16-bit timer (all channels)

—

IMIEB2

R/W

IMIEB1

R/W

IMIEB0

R/W

—

IMFB2

R/(W)

IMFB1

R/(W)

IMFB0

R/(W)

Input capture/compare match flag B0

[Clearing condition]

(Initial value)

Read IMFB0 when IMFB0=1, then write 0 in IMFB0.

[Setting conditions]

• TCNT0=GRB0 when GRB0 functions as an output

compare register.

• TCNT0 value is transferred to GRB0 by an input capture

signal when GRB0 functions as an input capture register.

Note:

* Only 0 can be written, to clear the flag.

Bit:

Initial value:

Read/Write:

Input capture/compare match flag B1

[Clearing condition]

(Initial value)

Read IMFB1 when IMFB1=1, then write 0 in IMFB1.

[Setting conditions]

• TCNT1=GRB1 when GRB1 functions as an output

compare register.

• TCNT1 value is transferred to GRB1 by an input capture

signal when GRB1 functions as an input capture register.

Input capture/compare match flag B2

[Clearing condition]

(Initial value)

Read IMFB2 when IMFB2=1, then write 0 in IMFB2.

[Setting conditions]

• TCNT2=GRB2 when GRB2 functions as an output

compare register.

• TCNT2 value is transferred to GRB2 by an input capture

signal when GRB2 functions as an input capture register.

Input capture/compare match interrupt enable B2

IMIB2 interrupt requested by IMFB2 flag is disabled

(Initial value)

IMIB2 interrupt requested by IMFB2 is enabled

Input capture/compare match interrupt enable B0

IMIB0 interrupt requested by IMFB0 flag is disabled

(Initial value)

IMIB0 interrupt requested by IMFB0 is enabled

Input capture/compare match interrupt enable B1

IMIB1 interrupt requested by IMFB1 flag is disabled

(Initial value)

IMIB1 interrupt requested by IMFB1 is enabled

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