H8SLASH3002 datasheet(113/700 Pages) RENESAS

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5.5 Usage Notes

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction

When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not

disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR,

MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant

when execution of the instruction ends the interrupt is still enabled, so its interrupt exception

handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception

handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.

This also applies to the clearing of an interrupt flag.

Figure 5-8 shows an example in which an IMIEA bit is cleared to 0 in the ITU.

Figure 5-8 Contention between Interrupt and Interrupt-Disabling Instruction

This type of contention will not occur if the interrupt is masked when the interrupt enable bit or

flag is cleared to 0.

IMIA exception handling

TIER write cycle by CPU

TIER address

Internal

address bus

Internal

write signal

IMIEA

IMIA

IMFA interrupt

signal

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